1. Field of the Invention
The present invention relates generally to a lateral-diffusion metal-oxide-semiconductor (LDMOS) device, and more particularly, to a LDMOS device having low On-state resistance (Ron).
2. Description of the Prior Art
With the progress of semiconductor integrated circuits manufacturing, it is more preferable to have controllers, memories, devices for low-voltage operation and power devices for high-voltage operation integrated in one single-chip system. Therefore the prior art has employed the insulated gate bipolar transistor (IGBT) and double-diffused metal oxide semiconductor (DMOS) transistor devices as the power devices of high-voltage operation in the single-chip system.
The DMOS transistor device can be categorized into the lateral DMOS (LDMOS) device and the vertical DMOS (VDMOS) device. Having advantage of higher operational bandwidth, higher operational efficiency, and convenience to be integrated with other devices such as CMOS devices due to its planar structure, LDMOS devices are more widely used. Please refer to FIGS. 1-2, wherein FIG. 1 is a schematic drawing illustrating a layout pattern of a conventional LDMOS transistor device and FIG. 2 is a cross-sectional view taken along a crossing line A-A′ in FIG. 1. As shown in FIGS. 1-2, the conventional LDMOS device 100 is a symmetric structure positioned on an N-type well 104 in a substrate 102. The LDMOS device 100 includes a gate 110 having a “” shape, a source 120 and a common drain 130. The source 120 includes a p-type doped region 122 having a high doping concentration and an N-type doped body 124 having a doping concentration formed in the p-type doped region 122. The common drain 130 is formed in a center area of the symmetric structure and includes a P-type doped region 132 having a high doping concentration. The gate 110 is positioned on a gate dielectric layer 112 and extends to a field oxide layer 114 that is formed by conventional local oxidation of silicon (LOCOS) method. Typically, another P-type doped region 116 having a high doping concentration is formed underneath the field oxide layer 116. In addition, it is well-known that a cell pitch of the conventional LDMOS device 100 is the length designated by the line A-A′.
Please refer to FIG. 3, which is a schematic drawing illustrating a portion of a layout pattern of a conventional source. The source 120a includes a P-type doped region 122a having a high doping concentration and an N-type doped body 124a having a high doping concentration positioned in the P-type doped region. As shown in FIG. 3, the N-type doped body 124a is a strip region formed in the P-type doped region 122a, therefore only two sides of the N-type doped body 124a contact with the P-type doped region 122a. Furthermore, butting contact 140 are usually used to electrically connect the P-type doped region 122a and the N-type doped body 124a that possess different conductive types to a same electrical potential. Therefore a width “a” of the stripe N-type doped body 124a, a distance “b” between the stripe N-type doped body 124a and the butting contact 140, and a distance “c” between the butting contact 140 and the gate 110 are always put in serious consideration when designing the circuit layout pattern. Accordingly, a distance “d” between any two parallel gates is a sum of the width “a” of the stripe N-type doped body 124a, the distance “2b” that represents the distances between the both sides of the N-type doped body 124a and the butting contact 140, and the distance “2c” that represents distances between the both sides of the butting contact 140 and the gate 110. As shown in FIG. 3, since the width “a”, the distances “2b” and the distance “2c” are spatially parallel and each width and distance is limited by its own process window, it is impossible to reduce the distance “d” between the parallel gates 110 according to this circuit layout pattern. For example, in the conventional process window, the width “a” of the stripe N-type doped body 124a is 0.6 micrometer (μm), the distance “b” of between the stripe N-type doped body 124a and the butting contact 140 is 0.5 μm, and the distance “c” between the butting contact 140 and the gate 110 is 0.3 μm, accordingly the distance “d” between the parallel gates 110 cannot be smaller than 2.2 μm.
As mentioned above, because the LDMOS device 100 is a high-voltage device that requires an operating voltage in a range of 20-300 Volt (V), the prior art always demands the LDMOS device 100 having high breakdown voltage and low Ron. For instance, The LDMOS device 100 having an operating voltage of 40V has required to have the cell pitch of 11 μm, the breakdown voltage of 49.5 V, and the Ron of 270 mΩ/mm2. It is well-known that due to the requirement of high breakdown voltage and the limitation of process window, the cell pitch of the LDMOS device 100 that horizontally formed on the substrate 102 cannot reduced as the single chip system keeps shrinking. Furthermore, such limitations is not only adverse to reduce the Ron but also adverse to the applicability of the LDMOS device 100.